Differential signaling techniques, which are also known as balanced input signaling techniques, have distinct advantages in providing immunity to noise pickup and crosstalk between channels. These techniques are often used for preventing false output due to noise or interference pickup at the input. For applications where the switching speed is high, the probability of noise influence is greater, and hysteresis becomes important for proper operation.
Referring to FIG. 1, a conventional prior art differential signal receiver 10 without hysteresis illustratively includes a current mirror biasing circuit formed by MOS transistors P1, N1 and P2. PMOS transistors P3 and P4 are the input transistors whose gates are connected to an input voltage IN and a reference voltage VREF, respectively. NMOS transistors N2 and N3 are the current mirror load transistors.
The source of the biasing PMOS transistor P1 is connected to VDD, while its gate and drain are connected together and to the gate of the PMOS transistor P2 and the drain of the NMOS transistor N1. The gate and drain of the NMOS transistor N1 are connected together, while its source is connected to ground. Since the drain and gate of the transistors P1 and N1 are shorted, these transistors always remain in saturation. The source of the PMOS transistor P2 is connected to VDD, while its drain is connected to the sources of the input PMOS transistors P3 and P4. The drains of the PMOS transistors P3 and P4 are connected to the drains of the NMOS transistors N2 and N3, respectively. The gates of the NMOS transistors N2 and N3 are connected together and to the drain of the NMOS transistor N2, while their sources are connected to ground.
The current mirror circuit provides a constant current through the receiver. When the input voltage IN is less than the reference voltage VREF, the resistance of the PMQS transistor P3 becomes less than that of the PMOS transistor P4. Therefore, the current in the input transistor branch (which includes the transistors P3 and N2) increases, while the current in the reference voltage transistor branch (which includes the transistors P4 and N3) decreases by an equal amount. This makes the output voltage VOUT_prior low. Similarly, when the input voltage IN is greater than the reference voltage VREF, the current in the P4-N3 transistor branch decreases, while that in the P3-N2 transistor branch increases by the same amount, and the output voltage VOUT_prior goes high. In this manner, the differential input receiver functions as a comparator whose trip point is set at the reference voltage VREF.
This type of differential input receiver is, however, susceptible to noise when the input voltage is close to the trip point of the differential input receiver. The influence of such noise can be seen in FIG. 2, which shows the waveforms for a conventional prior art differential receiver. As may be seen, the noise results in large false spikes which, in turn, results in incorrect functioning of the circuit.
Turning now additionally to FIG. 3, waveforms of a differential receiver without hysteresis and of a differential input receiver having hysteresis are shown. Whenever the input crosses the reference voltage (here 0.75V), the output V(OUT)_prior of a differential receiver without hysteresis switches. Yet, the output V(OUT) of a differential receiver with hysteresis goes high only when the input goes beyond VTH (here 0.84V), and it remains high until the input signal IN goes lower than VTL (here 0.66V), thereby providing a greater noise immunity.
Hysteresis enables suppression of the effect of noise by adjusting the threshold voltage based upon the output voltage, setting a higher threshold voltage VTH or a lower threshold voltage VTL, as shown in FIG. 4. The higher threshold voltage VTH is the threshold value when the output is low, while the lower threshold voltage VTL is the threshold value when the output is high. This arrangement ensures that the output goes low only when the input becomes greater than VTH, and will go high only when the input drops below the lower threshold VTL. This provides an input noise margin of VTH-VTL.
U.S. Pat. No. 5,796,281 describes a differential input receiver 30 with hysteresis, which is shown in FIG. 5. A PMOS transistor Q2 is connected in parallel with a reference voltage transistor Q1 to provide hysteresis. The input to the transistor Q2 is the output of the input stage Vout. Since the output of the input buffer is never at a strong logic low, significant hysteresis is only possible with a relatively large size transistor Q2. Furthermore, this circuit provides hysteresis only in one direction.
U.S. Pat. No. 5,666,068 describes a differential input receiver 40 with hysteresis as shown in FIG. 6. In this circuit, parallel transistors P8 and P9 are used to provide hysteresis. The inputs VIN1 and VIN2 are for the input signals of the receiver 40. Since this signal level is small here as well, the transistors P8 and P9 are required to be large in size to provide adequate hysteresis. In addition, this arrangement reduces the input impedance of the receiver 40.